加分考試

module aaa;
wire a,b,c,d;
wire c_out;
system_clock #400 clock(a);
system_clock #200 clock(b);
system_clock #100 clock(c);
system_clock #50 clock(d);
xxx t(c_out,a,b,c,d);
endmodule
module xxx(c_out,a,b,c,d);
input a,b,c,d;
output c_out;
wire w1,w2,w3,w4,w5,a_bar,b_bar,c_bar,d_bar;
not(a_bar,a);
not(b_bar,b);
not(c_bar,c);
not(d_bar,d);
and(w1,b,c_bar,d_bar);
and(w2,a_bar,b_bar,d);
and(w3,a_bar,b,c);
and(w4,b,c,d);
and(w5,b_bar,c_bar,d);
or(c_out,w1,w2,w3,w4,w5);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

四位元全加器

module top;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;
system_clock #200 clock1(x_in1);
system_clock #100 clock2(x_in2);
system_clock #50 clock3(x_in3);
system_clock #25 clock4(x_in4);
AOI_Unit m1(y_out,x_in1,x_in2,x_in3,x_in4);
endmodule
module AOI_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule
module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

一位元全加器練習

module top;
wire a,b,c_in;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #200 clock2(b);
system_clock #400 clock3(c_in);
test AH1(sum,c_out,a,b,c_in);
endmodule
module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule
module test(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
add_half M1(w1,w2,a,b);
add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule
module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/3) clk = ~clk;
#(PERIOD/3) clk = ~clk;
#(PERIOD/3) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

全加器練習

module top;
wire a,b,c_in;
wire sum,c_out;
system_clock #100 clockl(a);
system_clock #75 clock2(b);
system_clock #25 clock3(c_in);
Add_full K1(sum,c_out,a,b,c_in);
endmodule
module Add_full(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
Add_half M1(w1,w2,a,b);
Add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule
module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2) clk= ~clk;
#(PERIOD/2) clk= ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

半加法器練習

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
Add_half AH1(sum,c_out,a,b);
endmodule
module Add_half(sum,c_out, a, b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule
module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule